Current random-access memory (RAM) array designs (such as static-RAM (SRAM) arrays, dynamic-RAM (DRAM) arrays, etc.) experience high peak currents during pre-charging operations (e.g., wake-up or start-up operations). During normal operation, a RAM array only utilizes (e.g., discharges/charges) a predetermined number of bit-lines (BL) and complimentary bit-lines (BLB). For example, in some embodiments, RAM array is configured to read/write a maximum of 72 of the total number of bit-lines in the RAM array during a read/write operation (referred to herein as a two-multiplexer (2mux) design). As another example, in some embodiments, a RAM array is configured to read/write a maximum of about ¼ of the total bit-lines in the RAM array during a read/write operation (referred to herein as a four-multiplexer (4mux) design). The RAM array experiences a read/write peak current based on the maximum number of BLs and BLBs used during a read/write operation.
During a pre-charging operation (e.g., start-up/wake-up operation), each of the BLs and BLBs in the RAM array are charged, resulting in a charge peak current having value greater than the read/write peak current. Conventional memory units utilize a signal bit-line precharge stage that charges all of the BLs and BLBs in the RAM array from a sleep/off state to a charged state in a single charging cycle. The charge peak current during a charge operation can exceed, for example, 300 μA. The high charge peak currents can cause damage to one or more circuit elements in the RAM array and/or circuit elements connected to the RAM array.